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philips semiconductors programmable logic devices product specification plus16r8d/-7 series pal devices 16l8, 16r8, 16r6, 16r4 36 september 10, 1993 8531358 10777 features ? ultra high-speed t pd = 7.5ns and f max = 74mhz for the plus16r8-7 series t pd = 10ns and f max = 60 mhz for the plus16r8d series ? 100% functionally and pin-for-pin compatible with industry standard 20-pin pal ? ics ? power-up reset function to enhance state machine design and testability ? design support provided via snap and other cad tools for series 20 pal devices ? field-programmable on industry standard programmers ? security fuse ? individual 3-state control of all outputs description the philips semiconductors plus16xx family consists of ultra high-speed 7.5ns and 10ns versions of series 20 pal devices. the plus16xx family is 100% functional and pin-compatible with the 16l8, 16r8, 16r6, and 16r4 series devices. the sum of products (and-or) architecture is comprised of 64 programmable and gates and 8 fixed or gates. multiple bidirectional pins provide variable input/output pin ratios. individual 3-state control of all outputs and registers with feedback (r8, r6, r4) is also provided. proprietary designs can be protected by programming the security fuse. the plus16r8, r6, and r4 have d-type flip-flops which are loaded on the low-to-high transition of the clock input. in order to facilitate state machine design and testing, a power-up reset function has been incorporated into these devices to reset all internal registers to active-low after a specific period of time. the philips semiconductors state-of-the-art oxide isolation bipolar fabrication process is employed to achieve high-performance operation. the plus16xx family of devices are field programmable, enabling the user to quickly generate custom patterns using standard programming equipment. see the programmer chart for qualified programmers. the snap software package from philips semiconductors supports easy design entry for the plus16xx series as well as other pld devices from philips semiconductors. the plus16xx series are also supported by other standard cad tools for pal-type devices. order codes are listed in the ordering information table. device number dedicated inputs combinatorial outputs registered outputs plus16l8 10 8 (6 i/o) 0 plus16r8 8 0 8 plus16r6 8 2 i/o 6 plus16r4 8 4 i/o 4 ordering information description order code drawing number 20-pin plastic dual-in-line 300mil-wide plus16r8dn plus16r6dn plus16r4dn plus16l8dn plus16r87n plus16r67n plus16r47n plus16l87n 0408b 20-pin plastic leaded chip carrier (plcc) plus16r8da plus16r6da plus16r4da plus16l8da plus16r87a plus16r67a plus16r47a plus16l87a 0400e note: the plus16xx series of devices are also processed to military requirements for operation over the military temperature range. for specifications and ordering information, consult the philips semiconductors military data book. ? pal is a registered trademark of advanced micro devices, inc.
philips semiconductors programmable logic devices product specification plus16r8d/-7 series pal devices 16l8, 16r8, 16r6, 16r4 september 10, 1993 37 pin configurations 11 1 2 3 19 20 symbol description i dedicated input o dedicated combinatorial output q registered output b bidirectional (input/output) clk clock input oe output enable v cc supply voltage gnd ground symbol description i dedicated input o dedicated combinatorial output q registered output b bidirectional (input/output) clk clock input oe output enable v cc supply voltage gnd ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 d q q d q q d q q d q q d q q d q q d q q and or array d q q plus16r8 plus16l8 clk i 0 i 1 gnd i 2 i 3 i 4 i 5 i 6 i 7 oe q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 and or array i 0 i 1 i 2 gnd i 3 i 4 i 5 i 6 i 7 i 8 i 9 o 0 b 1 b 2 b 3 b 4 b 5 b 6 o 7 v cc plus16r8 plus16l8 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 v cc o 7 b 6 b 2 b 3 b 4 b 5 b 1 o 0 i 9 gnd i 8 i 3 i 4 i 5 i 6 i 7 i 2 i 1 i 0 and or array outputs 1 2 3 19 20 4 5 6 7 8 9 10 12 13 14 15 16 17 18 v cc q 7 q 6 q 2 q 3 q 4 q 5 q 1 q 0 gnd i 3 i 4 i 5 i 6 i 7 i 2 i 1 i 0 and or array outputs clk oe
philips semiconductors programmable logic devices product specification plus16r8d/-7 series pal devices 16l8, 16r8, 16r6, 16r4 september 10, 1993 38 pin configurations 11 symbol description i dedicated input o dedicated combinatorial output q registered output b bidirectional (input/output) clk clock input oe output enable v cc supply voltage gnd ground plus16r4 plus16r4 1 2 3 19 20 4 5 6 7 8 9 10 12 13 14 15 16 17 18 v cc b 7 b 6 q 2 q 3 q 4 q 5 b 1 b 0 gnd i 3 i 4 i 5 i 6 i 7 i 2 i 1 i 0 and or array outputs clk oe 11 symbol description i dedicated input o dedicated combinatorial output q registered output b bidirectional (input/output) clk clock input oe output enable v cc supply voltage gnd ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 d q q d q q d q q d q q d q q d q q and or array plus16r6 clk i 0 i 1 gnd i 2 i 3 i 4 i 5 i 6 i 7 oe b 0 q 1 q 2 q 3 q 4 q 5 q 6 b 7 v cc plus16r6 1 2 3 19 20 4 5 6 7 8 9 10 12 13 14 15 16 17 18 v cc b 7 q 6 q 2 q 3 q 4 q 5 q 1 b 0 gnd i 3 i 4 i 5 i 6 i 7 i 2 i 1 i 0 and or array outputs clk oe 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 d q q d q q d q q d q q and or array clk i 0 i 1 gnd i 2 i 3 i 4 i 5 i 6 i 7 oe b 0 b 1 q 2 q 3 q 4 q 5 b 6 b 7 v cc
philips semiconductors programmable logic devices product specification plus16r8d/-7 series pal devices 16l8, 16r8, 16r6, 16r4 september 10, 1993 39 logic diagram plus16l8 notes: 1. all unprogrammed or virgin aando gate locations are pulled to logic a0o. 2. programmable connections. 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 i 0 i 1 i 2 i 3 i 4 i 5 i 6 i 7 i 8 i 9 o 0 product terms (063) b 1 b 2 b 3 b 4 b 5 b 6 o 7 inputs (031) 0 31 0 7 8 16 15 23 24 31 32 39 40 47 48 55 56 63
philips semiconductors programmable logic devices product specification plus16r8d/-7 series pal devices 16l8, 16r8, 16r6, 16r4 september 10, 1993 40 logic diagram plus16r8 notes: 1. all unprogrammed or virgin aando gate locations are pulled to logic a0o. 2. programmable connections. 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 clk i 0 i 1 i 2 i 3 i 4 i 5 i 6 i 7 oe q 0 product terms (063) q 1 q 2 q 3 q 4 q 5 q 6 q 7 inputs (031) 0 31 0 7 8 16 15 23 24 31 32 39 40 47 48 55 56 63 d q q d q q d q q d q q d q q d q q d q q d q q
philips semiconductors programmable logic devices product specification plus16r8d/-7 series pal devices 16l8, 16r8, 16r6, 16r4 september 10, 1993 41 logic diagram plus16r6 notes: 1. all unprogrammed or virgin aando gate locations are pulled to logic a0o. 2. programmable connections. 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 clk i 0 i 1 i 2 i 3 i 4 i 5 i 6 i 7 oe b 0 product terms (063) q 1 q 2 q 3 q 4 q 5 q 6 b 7 inputs (031) 0 31 0 7 8 16 15 23 24 31 32 39 40 47 48 55 56 63 d q q d q q d q q d q q d q q d q q
philips semiconductors programmable logic devices product specification plus16r8d/-7 series pal devices 16l8, 16r8, 16r6, 16r4 september 10, 1993 42 logic diagram plus16r4 notes: 1. all unprogrammed or virgin aando gate locations are pulled to logic a0o. 2. programmable connections. 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 clk i 0 i 1 i 2 i 3 i 4 i 5 i 6 i 7 oe b 0 product terms (063) b 1 q 2 q 3 q 4 q 5 b 6 b 7 inputs (031) 0 31 0 7 8 16 15 23 24 31 32 39 40 47 48 55 56 63 d q q d q q d q q d q q
philips semiconductors programmable logic devices product specification plus16r8d/-7 series pal devices 16l8, 16r8, 16r6, 16r4 september 10, 1993 43 functional descriptions the plus16xx series utilizes the familiar sum-of-products implementation consisting of a programmable and array and a fixed or array . these devices are capable of replacing an equivalent of four or more ssi/msi integrated circuits to reduce package count and board area occupancy, consequently improving reliability and design cycle over standard cell or gate array options. by programming the security fuse, proprietary designs can be protected from duplication. the plus16xx series consists of four pal-type devices. depending on the particular device type, there are a variable number of combinatorial and registered outputs available to the designer . the plus16l8 is a combinatorial part with 8 user configurable outputs (6 bidirectional), while the other three devices, plus16r8, plus16r6, plus16r4, have respectively 8, 6, and 4 output registers. 3-state outputs the plus16xx series devices also feature 3-state output buffers on each output pin which can be programmed for individual control of all outputs. the registered outputs (qn) are controlled by an external input (/oe), and the combinatorial outputs (on, bn) use a product term to control the enable function. programmable bidirectional pins the plus16xx products feature variable input/output ratios. in addition to 8 dedicated inputs, each combinatorial output pin of the registered devices can be individually programmed as an input or output. the plus16l8 provides 10 dedicated inputs and 6 bidirectional i/o lines that can be individually configured as inputs or outputs. output registers the plus16r8 has 8 output registers, the 16r6 has 6, and the 16r4 has 4. each output register is a d-type flip-flop which is loaded on the low-to-high transition of the clock input. these output registers are capable of feeding the outputs of the registers back into the array to facilitate design of synchronous state machines. power-up reset by resetting all flip-flops to a logic low , as the power is turned on, the plus16r8, r6, r4 enhance state machine design and initialization capability. software support like other programmable logic devices from philips semiconductors, the plus16xx series are supported by slice, the pc-based software development tool from philips semiconductors. the plus16xx family of devices are also supported by standard cad tools for pal devices, including abel and cupl. slice is available free of charge to qualified users. logic programming the plus16xx series is fully supported by industry standard (jedec compatible) pld cad tools, including philips semiconductors snap design software package. abel ? cupl ? and palasm ? 90 design software packages also support the plus16xx architecture. all packages allow boolean and state equation entry formats. snap, abel and cupl also accept, as input, schematic capture format. programming/software support ref to section 9 (development software) and section 10. (third-party programmer/ software support ) of the pld data handbook for additional information. and array (i, b) i, b i, b p, d i, b state inactive 1, 2 code o i, b i, b p, d i, b state code h i, b i, b p, d i, b state code l i, b i, b p, d i, b state code i, b i, b don't care virgin state a factory shipped virgin device contains all fusible links intact, such that: 1. all outputs are at aho polarity. 2. all p n terms are disabled. 3. all p n terms are active on all outputs. abel is a trademark of data i/o corp. cupl is a trademark of logical devices, inc. palasm is a registered trademark of amd corp.
temperature maximum junction maximum ambient allowable thermal rise ambient to junction 150 c 75 c 75 c philips semiconductors programmable logic devices product specification plus16r8d/-7 series pal devices 16l8, 16r8, 16r6, 16r4 september 10, 1993 44 absolute maximum ratings 1 thermal ratings ratings symbol parameter min max unit v cc supply voltage 0.5 +7 v dc v in input voltage 1.2 +8.0 v dc v out output voltage 0.5 v cc + 0.5v v dc i in input currents 30 +30 ma i out output currents +100 ma t stg storage temperature range 65 +150 c note: 1. stresses above those listed may cause malfunction or permanent damage to the device. this is a stress rating only . functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. operating ranges ratings symbol parameter min max unit v cc supply voltage +4.75 +5.25 v dc t amb operating freeair temperature 0 +75 c
philips semiconductors programmable logic devices product specification plus16r8d/-7 series pal devices 16l8, 16r8, 16r6, 16r4 september 10, 1993 45 dc electrical characteristics 0 c t amb +75 c, 4.75 v cc 5.25v limits symbol parameter test conditions min typ 1 max unit input voltage 2 v il low v cc = min 0.8 v v ih high v cc = max 2.0 v v ic clamp v cc = min, i in = 18ma 0.8 1.5 v output voltage v cc = min, v in = v ih or v il v ol low i ol = 24ma 0.5 v v oh high i oh = 3.2 ma 2.4 v input current v cc = max i il low 3 v in = 0.40v 250 m a i ih high 3 v in = 2.7v 25 m a i i maximum input current v in = v cc = v ccmax 100 m a output current v cc = max i ozh output leakage v out = 2.7v 100 m a i ozl output leakage v out = 0.4v 100 m a i os short circuit 4, 5 v out = 0v 30 90 ma i cc v cc supply current v cc = max 160 180 ma capacitance 6 c in input v cc = 5v v out = 2.0v 8 pf c b i/o (b) v out = 2v, f = 1mhz 8 pf notes: 1. all typical values are at v cc = 5v, t amb = +25 c. 2. all voltage values are with respect to network ground terminal. 3. leakage current for bidirectional pins is the worst case of i il and i ozl or i ih and i ozh . 4. test one at a time. 5. duration of short circuit should not exceed 1 second. 6. these parameters are not 100% tested but periodically sampled.
philips semiconductors programmable logic devices product specification plus16r8d/-7 series pal devices 16l8, 16r8, 16r6, 16r4 september 10, 1993 46 ac electrical characteristics r 1 = 200 w , r 2 = 390 w , 0 c t amb +75 c, 4.75 v cc 5.25v limits symbol parameter from to 7 d unit min 1 typ max min 1 max pulse width t ckh clock high ck+ ck 5 7 ns t ckl clock low ck ck+ 5 7 ns t ckp period ck+ ck+ 10 14 ns setup & hold time t is input input or feedback ck+ 7 9 ns t ih input ck+ input or feedback 0 0 ns propagation delay t cko clock ck q 3 6.5 3 7.5 ns t ckf clock 3 ck q 3 6.5 ns t pd output (16l8, r6, r4) 2 i, b output 3 7.5 3 10 ns t oe1 output enable 4 oe output enable 3 8 3 10 ns t oe2 output enable 4,5 i output enable 3 10 3 10 ns t od1 output disable 4 oe output disable 3 8 3 10 ns t od2 output disable 4,5 i output disable 3 10 3 10 ns t skw output q q 1 1 ns t ppr power-up reset v cc + q+ 10 10 ns frequency (16r8, r6, r4) no feedback 1/ (t ckl + t ckh ) 6 100 71.4 mhz f max internal feedback 1/ (t is + t ckf ) 6 90 64.5 mhz external feedback 1/ (t is + t cko ) 6 74 60.6 mhz * for definitions of the terms, please refer to the t iming/frequency definitions tables. notes: 1. cl = 0pf while measuring minimum output delays. 2. t pd test conditions: cl = 50pf (with jig and scope capacitance), v ih = 3v, v il = 0v, v oh = v ol = 1.5v. 3. t ckf was calculated from measured internal f max . 4. for 3-state output; output enable times are tested with c l = 50pf to the 1.5v level, and s 1 is open for high-impedance to high tests and closed for high-impedance to low tests. output disable times are tested with c l = 5pf. high-to-high impedance tests are made to an output voltage of v t = (v oh 0.5v) with s 1 open, and low-to-high impedance tests are made to the v t = (v ol + 0.5v) level with s 1 closed. 5. same function as t oe1 and t od1, with the dif ference of using product term control. 6. not 100% tested, but calculated at initial characterization and at any time a modification in design takes place which may af fect the frequency.
philips semiconductors programmable logic devices product specification plus16r8d/-7 series pal devices 16l8, 16r8, 16r6, 16r4 september 10, 1993 47 test load circuit +5v c l r 1 r 2 s 1 c 2 c 1 note: c 1 and c 2 are to bypass v cc to gnd. v cc gnd clk i n i 0 b 0 /o 0 q n dut b n /o n q 0 oe inputs output register skew t skw 1.5v 1.5v 3v 0v 3v 0v 3v 0v clk q n (registered output) q n + 1 (registered output) clock to feedback path clk d t is t ckf q
????? ????? ????? ????? ????? ????? ????? ????? ????? ???? ???? ???? ???? ??????? ??????? ??????? ??????? 1.5v 1.5v 1.5v 1.5v 1.5v 1.5v v t 1.5v 1.5v +3v 0v +3v 0v v oh v ol +3v 0v i, b (inputs) clk q (registered outputs) oe t ih t is t is t ckh t ckl t ckp t cko t od1 t oe1 flip-flop outputs i, b (inputs) o, b (combinatorial outputs) i, b (output enable) t pd t oe2 t od2 1.5v 1.5v +1.5v +1.5v v t +3v 0v v oh v ol +3v 0v gate outputs 1.5v 1.5v 1.5v 1.5v 1.5v 1.5v 1.5v 0v v oh v ol +3v 0v +3v 0v v cc 4.5v v cc q (registered outputs) i, b (inputs) clk t ppr t cko t ih t is t is t ckh t ckl t is+ t ckf powerup reset philips semiconductors programmable logic devices product specification plus16r8d/-7 series pal devices 16l8, 16r8, 16r6, 16r4 september 10, 1993 48 timing diagrams 1, 2 notes: 1. input pulse amplitude is 0v to 3v . 2. input rise and fall times are 2.5ns. timing definitions symbol parameter t ckh width of input clock pulse. t ckl interval between clock pulses. t ckp clock period. t is required delay between beginning of valid input and positive transition of clock. t ih required delay between positive transition of clock and end of valid input data. t ckf delay between positive transition of clock and when internal q output of flip-flop becomes valid. t cko delay between positive transition of clock and when outputs become valid (with oe low). t oe1 delay between beginning of output enable low and when outputs become valid. t od1 delay between beginning of output enable high and when outputs are in the off-state. t oe2 delay between predefined output enable high, and when combinational outputs become valid. t od2 delay between predefined output enable low and when combinational outputs are in the off-state. t ppr delay between v cc (after power-on) and when flip-flop outputs become preset at a1o (internal q outputs at a0o). t pd propagation delay between combinational inputs and outputs. frequency definitions f max no feedback: determined by the minimum clock period, 1/(t ckl + t ckh ). internal feedback: determined by the internal delay from flip-flop outputs through the internal feedback and array to the flip-flop inputs, 1/(t is + t ckf ). external feedback: determined by clock-to-output delay and input setup time, 1/(t is + t cko ).
philips semiconductors programmable logic devices product specification plus16r8d/-7 series pal devices 16l8, 16r8, 16r6, 16r4 september 10, 1993 49 output register preload v oh registered i/o input output ?? ?? ?? ?? v ol v ih v il v ihh v il v ih v il pin 1 clock pin 11 oe t d t su t w t d t d note: t d = t su = t w = 100ns to 1000ns. v ihh = 10.25v to 10.75v. the output registers can be preloaded to any desired state during device testing. this permits any state to be tested without having to step through the entire state-machine sequence. each register is preloaded individually by following the steps given below . step 1. with v cc at 5v and pin 1 at v il , raise pin 11 to v ihh . step 2. apply either v il or v ih to the output corresponding to the register to be preloaded. step 3. pulse pin 1, clocking in preload data. step 4. remove output voltage, then lower pin 1 1 to v il . preload can be verified by observing the voltage level at the output pin. pin number references for dip package.
philips semiconductors programmable logic devices product specification plus16r8d/-7 series pal devices 16l8, 16r8, 16r6, 16r4 september 10, 1993 50 programming/software refer to section 9 ( development software ) and section 10 ( third-party programmer/software support ) of this data handbook for additional information. snap resource summary designations i0 i9 10 dinpal7 ninpal7 programmable and array and or noutpal7 o0, o7 8 1 or noutpal7 b1 b6 8 1 ninpal7 dinpal7 plus16l8 i0 i7 8 dinpal7 ninpal7 programmable and array and or dffpal7 q0 8 ninpal7 dinpal7 clk ckpal7 oe noepal7 d q q or 8 d q q dffpal7 noutpal7 noutpal7 q7 plus16r8
philips semiconductors programmable logic devices product specification plus16r8d/-7 series pal devices 16l8, 16r8, 16r6, 16r4 september 10, 1993 51 snap resource summary designations (continued) i0 i7 8 dinpal7 ninpal7 programmable and array and or b0, b7 8 ninpal7 dinpal7 clk ckpal7 oe noepal7 d q q or 8 dffpal7 noutpal7 noutpal7 q1 q6 1 plus16r6 plus16r4 i0 i7 8 dinpal7 ninpal7 programmable and array and or b0, b1, b6, b7 8 ninpal7 dinpal7 clk ckpal7 oe noepal7 d q q or 8 dffpal7 noutpal7 noutpal7 q2 q5 1

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